Compute Express Link (CXL)
An open interconnect standard built on the PCI Express physical layer that links processors, accelerators and memory devices with cache coherency; the ISC2 outline names it as a converged protocol.
Compute Express Link is an open interconnect standard, developed by the CXL Consortium, with its first version released in 2019, that runs over the physical and electrical layer of PCI Express. It connects processors to accelerators and memory expansion devices, and lets them share memory with cache coherency. It combines three protocols on one link: CXL.io for input and output, CXL.cache for a device to cache host memory, and CXL.mem for a host to use memory attached to a device. Later versions add switching, so memory can be pooled across several hosts and assigned to whichever needs it.
The ISC2 exam outline names it among the converged protocols, beside iSCSI, Voice over IP and InfiniBand over Ethernet: traffic that once needed separate buses now travels together over one interconnect. Memory shared or pooled between hosts has to stay isolated so one host cannot read another’s data, and the link itself becomes something to protect. Later versions of the specification add optional link encryption and integrity checking for that reason.
Exam relevance: questions in this area tend to stay at recognition level. Candidates are expected to know that CXL is a converged interconnect for processors and memory inside and between servers, not a wide-area network protocol, and that sharing memory raises isolation concerns.